Hello! 👋

I'm Valentino Guerrini

Computer Engineering Student

About Me

I am a graduate researcher pursuing a dual Master's in Computer Science at the University of Illinois Chicago and Computer Engineering at Politecnico di Milano. My work spans high-performance computing, reconfigurable architectures, and applied cryptography, with a focus on optimizing MPI communication algorithms and developing FPGA accelerators for homomorphic encryption. I have experience with both edge devices (Kria KV260) and datacenter platforms (Versal VCK5000, AMD Alveo U55C), and my broader interests lie at the intersection of algorithms, hardware design, and distributed systems to make computation faster, more secure, and more efficient.

Verilog C C++ Java Vivado Vitis FPGAs Cryptography

Projects

01

Homomorphic Encryption Acceleration Through Reconfigurable Fabric

Developed FPGA accelerator for homomorphic encryption, achieving significant speedups for small polynomials and integrating with Full-RNS HEAAN, Finalist in AMD Open Hardware 2024

VerilogC++FPGA DesignXRTVitisCryptography
02

Autonomous Visual Inspection Tungsten-Based Coating

Developed in collaboration with Collins Aerospace a hybrid AI-mechatronic system to automate visual inspection of HVOF-coated aerospace rods, achieving >97% scratch detection accuracy and reducing manual workload through automated rod rotation.

Machine LearningAutomationComputer VisionEmbedded SystemsMultidisciplinary
03

QuErK: Accelerating Quantum Error Correction through FPGAs

FPGA Based Accelerator for Sparse Blossom Algorithm for Quantum Error Correction on AMD U55C FPGA, achieving a top speedup of 49x with respect to software.

VerilogC++FPGA DesignXRTVitisQuantum Computing
04

DPA Attack resistant SHA-3 Algorithm for Cortex-M4 Microcontrollers

Implemented the Ishai-Sahai-Wagner (ISW) protection scheme to safeguard the Secure Hash Algorithm 3 (SHA-3) against Differential Power Analysis (DPA) attacks on ARM Cortex M4 microcontrollers.

C/C++STM32Embedded Systems ProgrammingApplied CryptographySide-Channel Attack Countermeasures
05

MyShelfie - Java Multiplayer Board Game

Developed a full Java implementation of the MyShelfie board game with both GUI and networked multiplayer using RMI and sockets. Designed a resilient client-server architecture supporting chat, CLI, and fault tolerance.

JavaRMISocketsMultiplayerJavaFXOOPDesign PatternsSoftware DesignConcurrencyVersion Control

Publications

01

[IPDPSW] Towards the Acceleration of the Sparse Blossom Algorithm for Quantum Error Correction

M. Venere, V. Guerrini, B. Branchini, D. Conficconi, D. Sciuto and M. D. Santambrogio

Experience

Research Assistant

HPCLab, University of Illinois Chicago

Jan 2025 - Present
  • Researching MPI AllReduce optimizations for high-performance computing.
  • Achieved 3.5× speedup over MPICH with a runtime-configurable Allgather algorithm for small–medium messages.
  • Developing an enhanced Reduce-Scatter integration to further optimize AllReduce.

Student Researcher

NECSTLab, Politecnico di Milano

Oct 2022 - Present
  • Developed ReFHE-NTT FPGA accelerator integrated into Full-RNS HEAAN, enabling arbitrary-size CKKS polynomials with up to 4.5× speedup.
  • Developed FPGA architecture for CKKS achieving up to 2149× speedup (KV260) and 798× (VCK5000) for small polynomials over CPU baselines
  • Achieved a 2.75x speedup by accelerating the Sparse Blossom Algorithm for Quantum Error Correction on an AMD Alveo U55C FPGA

Advanced Research Intern

STMicroelectronics

Sep 2023 - Jan 2024
  • Joined the SRA security team in the Advanced Research department, focusing on cryptography and embedded systems.
  • Conducted a detailed analysis of performance-memory trade-offs in microcontroller applications for different zero-knowledge protocols
  • Coordinated with a team of 20+ researchers from both academia and industry

Education

Master of Science in Computer Science

University of Illinois Chicago

2024 - 2025
  • GPA: 3.71
  • Double Degree Program with Politecnico di Milano
  • Thesis on High-Performance Computing, MPI AllReduce optimizations

Master of Science in Computer Science and Engineering

Politecnico di Milano

2023 - 2026
  • GPA: 27.56/30
  • Thesis on FPGA acceleration of CKKS Homomorphic Encryption Scheme

Multidisciplinary honour program

Alta Scuola Politecnica

2023 - 2025
  • Selective honors program by Politecnico di Milano and Politecnico di Torino for top Master's students
  • Focused on interdisciplinary innovation and complex problem-solving

Bachelor of Science in Computer Engineering

Politecnico di Milano

2020 - 2023
  • Graded 108/110